RISC-V CPU IP Solution
RISC-V CPU IP Solution
| Highlights of UX1000 Processor | |||
| Pipeline | Out-of-Order 12-pipeline | ||
| Decode Width | Configurable 3, 4 or 6-wide decode | ||
| Issue-Width | Configurable up to 8 integer instructions and 3 vector instructions | ||
| Privilege Modes | Machine, Hypervisor, Supervisor, User | ||
| ISA | RV64IMAFDCVBZfh | ||
| Bit Manipulation | Zba + Zbb + Zbc + Zbs | ||
| Floating Point | Zfh(Half precision), F (Single precision) and D(Double precision) | ||
| Vector Extension | RISC-V Vector 1.0 Version (Up to Date) | ||
| Memory Addressing | Virtual addressing Sv39, Sv48 | ||
| Instruction Subsystem | Instruction Cache , ILM, Private L2 Cache, Cluster Cache | ||
| Data Subsystem | Data Cache, DLM , Private L2 Cache, Cluster Cache | ||
| SoC Connectivity | AXI Mem Bus, AHB-Lite Peripheral Bus, AXI Slave Port, AXI IO Coherence Port | ||
| Multi-core Configurations | Support single cluster and multi-cluster configuration, each cluster can have up to 8 cores | ||
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