NI900 is a DSA processor based on 900 Series. NI900 is optimized with features specifically targeting AI applications.
Base Processor: Can be configured into any RV32 or RV64 processor ---N900/U900/NX900/UX900.
RVV1.0 VPU: Support VPU based on RISC-V V Extension (RVV1.0 Vector ISA), with 512-bit to 1024-bit VLEN configurable.
Lite-VPU: VPU can be configured to Lite-VPU, supporting frequently used embedded AI vector instructions and data types to save VPU area.
Shared VPU across Multiple Cores: Multiple cores within one cluster can share one VPU while keeping software consistent in a SMP architecture to save area.
NPU Accelerator: Can be tightly coupled with CPU through NI900's IOCP(IO Coherent Port) to maintain cache coherence with CPU.
User Defined Instruction Interface: Users can add customized scalar/vector instructions through Nuclei NICE interface, maintaining coherency with main CPU core.
RISC-V Vector Instruction Overview
RISC-V has released standard Vector Extension.
Vector extension has dedicated register file and load/store instructions. Vector length can be configured and is good for application that needs high parallel computing power.
SIMD processes more data with a single instruction compared to SISD.
RISC-V Vector is created for image and singal processing applications.
Can widen the the register file width for better parallel data processing capability.
RISC-V Vector(RVV) 1.0 Standard
Vector is one of the most important extensions of the RISC-V standard. RVV was kicked of in 2015 and released officially in 2021.
RVV 1.0 supports various data and computing type and can be dynamically configured. Same set of instructions can be deployed for different micro-architecture without modification.
RSIC-V GCC already supports RVV 1.0 starting from 10.2. The corresponding intrinsic API of GCC13 is updated to the newest v0.12 verson, and partially supports vectorization; GCC's support for vectorization is expected to be comprehensive when GCC14 is released.
The RISC-V CLANG17 version also supports the latest v0.12 version of intrinsic API, enabling automatic vectorization.
Starting from RISC-V Linux version 5.18, support for RVV has been introduced, and various computation libraries and middleware have rapidly adopted RVV1.0.
