900 Series 32/64-Bit High Performance Processor In Progress)  
N900 is 32bit, NX900 is 64bit, UX900 is 64bit +MMU. The dual-mode is  
designed for embedded applications that requires high-performance,  
real-time, cost-effective processing, e.g. AIoT edge computing. It is a  
good replacement for ARM Cortex-M7/M55, Cortex-R4/R5, Coretex-  
A7/A9/A35/A53.  
N/NX/UX 900 Core Complex  
DEBUG  
N/NX/UX 900 Core  
VPU  
MMU  
NMI  
ECLIC  
TIMER  
WFI/WFE  
NICE  
Vector  
MUL/DIV  
9
-Stage
Dual-issue  
High Real-Time  
Performance  
Security  
P, TEE)  
SP/DP FPU  
& DSP  
RV32/64  
I/M/A/C/V  
900 uCore  
I/D-Cache  
I/D-Cache  
ILM  
L2 Cache  
TEE  
PMP  
AXI  
6
4-bit AXI &  
ILM, DLM  
Interfaces  
NICE  
Extension  
Low Laten Full Development  
Interrupt  
Toolkit  
RISC-V  
Standard Debug  
-wire JTAG  
DLM0/DLM1  
AHB-Lite  
Interrupt  
ECLICEnhanced Core Level Interrupt Controller)  
ISA  
RISC-V RV32/64 I/M/A/C/F/D/P/V ISA supported  
RISC-V standard interrupts supported, including software,  
timer and external interrupts  
CPU Core  
9-Stage Pipeline, dual-issue  
Configurable interrupt numbers, levels and priorities  
Vectored fast interrupts supported  
Configurable Dynamic Branch Prediction unit  
Configurable Prefetch Unit  
Nested interrupts supported  
Privileged  
Modes  
Machine-Mode supported  
User-Mode supported  
Interrupt tail-chaining supported  
NMI  
VPU  
FPU  
DSP  
NMI (Non-Maskable Interrupt) supported  
Supervisor-Mode supported  
Configurable vlength VFPU based on V-extensions  
Single/double-precision supported (F, D extensions)  
Caches  
I-Cache, configurable Cache size, N-way, Cache Line Size 32Bytes  
D-Cache, configurable Cache size, 2-way, Cache Line Size 32Bytes  
L2-Cache, configurable Cache size  
SIMDPartial-SIMD64-bit and Non-SIMD DSP instructions (P  
extension)  
Bus Interfaces  
64/128-Bit AXI System Bus Interface  
32-Bit AHB-lite (Private Peripheral Interface)  
64-Bit ILM Bus Interface  
MMU  
Configurabel MMU (memory management unit)  
Supported 2-level TLBs, configurable TLB entries  
Low Power  
64-Bit AXI Slave Port  
WFIWait For Interruptand WFEWait For Event)  
Supported  
2 32-Bit DLM Bus Interface  
Sleep and Deep Sleep Mode Supported  
Debug  
Standard IEEE 4-wire JTAG supported  
Configurable Hardware Breakpoints  
NICE  
Allowing customers to add user-defined instructions  
Implementing application specific hardware co-unit based  
on NICE interface  
Extension  
Security  
Configurable PMP (Physical Memory Protection) feature  
Configurable TEE (Trusted Execution Environment) feature  
Tool Kit  
Standard RISC-V Toolchain supported  
Timer  
Configurable 64-bit private timer  
Linux/Windows IDE (Integrated Development Environment)  
supported