N300 Series Low Power Processor
N300 Series is designed for high-performance embedded applications, especially
N300 Core
JTAG/
-Wires JTAG
WFI/WFE
DEBUG
ECLIC
FPU
2
NMI
TIMER
DSP
NICE
Best energy
efficiency
Security
(PMP, TEE)
SP/DP FPU
& DSP
RV32
I/E/M/A/C/F/D/P
3-Stage Pipeline
I-Cache
N300 uCore
PMP
ILM
TEE
DLM
APB
MUL/DIV
I-Cache
Fast-IO
32-bit AHB-Lite &
NICE
Extension
4
-wire &
RISC-V
Standard Debug
Low Latency Full Development
Interrupt
Toolkit
3
2-bit APB
2
-wire JTAG
Fast-IO, ILM, DLM
Interfaces
AHB-Lite
N300 Series is also highly configurable, including single-precision and double-precision FPU, DSP (based on P extension
proposal) allowing customers to add or remove hardware feature to optimize for their SoC. Here are 3 typical configurations:
Comparison to Cortex-M3
(Higher Frequency than N205)
Comparisons to Cortex-M4/M4F
Comparisons to Cortex-M33
•
RV32 IMAC/EMAC supported
• Key configurations
• User mode & PMP
•
•
RV32 IMAC/EMAC supported
Key configurations
•
•
RV32 IMAC/EMAC supported
Key configurations
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•
RV32 IMAC/EMAC supported
Key configurations
•
•
•
•
•
•
•
•
•
•
User mode & PMP
I-Cache
• I-Cache
•
•
•
•
•
•
•
•
User mode & PMP
I-Cache
•
•
•
•
•
User mode & PMP
I-Cache
• D-Cache
ILM/DLM Interface
NICE Interface for extension
Fast-IO Interface
Single-Precision FPU
Double-Precision FPU
DSP
• ILM/DLM Interface
• NICE Interface for extension
• Fast-IO Interface
• Single-Precision FPU
• Double-Precision FPU
• DSP
ILM/DLM Interface
NICE Interface for extension
Fast-IO Interface
Single-Precision FPU
Double-Precision FPU
DSP
ILM/DLM Interface
NICE Interface for extension
Fast-IO Interface
Supervisor mode
S-PMP TEE
• Supervisor mode
• S-PMP TEE
ISA
Timer
•
RISC-V RV32 I/M/A/C/F/D/P ISA supported
Configurable 64-bit private timer
CPU Core
Interrupt
•
•
•
3-Stage Pipeline
ECLIC(Enhanced Core Level Interrupt Controller)
Configurable Branch Prediction unit
Configurable Prefetch Unit
•
RISC-V standard interrupts supported, including software,
timer and external interrupts
Privileged
Modes
• Configurable interrupt numbers, levels and priorities
•
•
•
Machine-Mode supported
User-Mode supported
•
•
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Vectored fast interrupts supported
Nested interrupts supported
Supervisor-Mode supported
Interrupt tail-chaining supported
Caches
•
•
I-Cache, configurable Cache size, 2-way, Cache Line Size 32Bytes
D-Cache, configurable Cache size, 2-way, Cache Line Size 32Bytes
NMI
FPU
DSP
•
•
NMI (Non-Maskable Interrupt) supported
Single/double-precision supported (F, D extensions)
Bus Interfaces
•
•
•
•
•
32-Bit AHB-Lite System Bus Interface
32-Bit AHB-Lite I-Cache Bus Interface
32-Bit APB PPI (Private Peripheral Interface)
32-Bit ILM, DLM Bus Interface
SIMD,Partial-SIMD,64-bit and Non-SIMD DSP
instructions (P extension)
NICE
Extension
•
•
Allowing customers to add user-defined instructions
Implementing application specific hardware co-unit
based on NICE interface
32-Bit Fast-IO Interface
Debug
•
•
4-wire & 2-wire JTAG supported
Configurable Hardware Breakpoints
Safety
•
Dual Core Lock-Step (separate license)
Security
• Parity/ECC protection on Memory/Bus interfaces
separate license)
•
•
•
Configurable PMP (Physical Memory Protection) feature
Configurable TEE (Trusted Execution Environment) feature
Configurable SCP (Side Channel Protection) feature
separate license)
(
Tool Kit
• Standard RISC-V Toolchain supported
• Linux/Windows IDE (Integrated Development
Environment) supported
(
Low Power
•
•
WFI(Wait For Interrupt)and WFE(Wait For Event)Supported
Sleep and Deep Sleep Mode Supported
N300 Series Diagram
JTAG
DEBUG
Core Wrapper
TIMER
…
Core
Extend
Instructions
ECLIC
IRQ
Misc Ctrl
NICE IF
NMI
N300 Series uCore
I-IF
D-IF
I-Cache D-Cache
LM Ctrl
BIU
I-Cache Bus IF
(
AHBLite)
System Bus IF
(AHBLite)
Fast-IO IF
(Single-Cycle)
ILM Master IF
(AHBLite/SRAM)
LM Master IF
(AHBLite/SRAM)
Private Peripheral IF
(APB)
Fast-IO
Modules
Peripheral Bus
System Bus
ILM
DLM
Ext
MEM
Per
1
Per
2
Per
3
SRAM