UX600 Series 64-Bit High Performance Processor
UX600 Series (64bit) with MMU is the entry-level application processors
UX600 Core Complex
UX600 Core
DEBUG
for AIoT edge computing. It is a good replacement for ARM Cortex-
MMU
NMI
ECLIC
TIMER
DSP
WFI/WFE
NICE
FPU
MUL/DIV
High Real-Time
Performance
Machine, User,
Supervisor-Mode
Security
(PMP, TEE)
RV64
I/M/A/C/F/D/P
6-Stage Pipeline
I/D-Cache
UX600 uCore
I-Cache
ILM
D-Cache
TEE
PMP
AXI
6
4-bit AXI &
ILM, DLM
Interfaces
4
-wire &
NICE
Extension
Low Latency Full Development
Interrupt
Toolkit
RISC-V
Standard Debug
2
-wire JTAG
DLM0/DLM1
AHB-Lite
UX600 Series is also highly configurable for customers to add or remove hardware feature to optimize for their SoC.
Here are the 3 typical configurations:
RV64 IMAC supported
64-bit AXI System Bus Interface
Key configurations
RV64 IMAC supported
64-bit AXI System Bus Interface
Key configurations
RV64 IMAC supported
64-bit AXI System Bus Interface
Key configurations
User mode & PMP
Multi-cycle Multiplier/Divider
64-bit ILM & 2 32bit DLM Interfaces
NICE Interface for extension
32-bit AHB-lite Private Peripheral Interface
64-bit AXI Slave Port
I-Cache
User mode & PMP
User mode & PMP
Multi-cycle Multiplier/Divider
64-bit ILM & 2 32bit DLM Interfaces
NICE Interface for extension
32-bit AHB-lite Private Peripheral Interface
64-bit AXI Slave Port
I-Cache
Multi-cycle Multiplier/Divider
64-bit ILM & 2 32bit DLM Interfaces
NICE Interface for extension
32-bit AHB-lite Private Peripheral Interface
D-Cache
64-bit AXI Slave Port
I-Cache
MMU
Single-Precision FPU
Double-Precision FPU
DSP
D-Cache
D-Cache
MMU
MMU
Single-Precision FPU
Double-Precision FPU
DSP
Supervisor mode
S-PMP TEE
Interrupt
ISA
ECLICEnhanced Core Level Interrupt Controller
RISC-V RV64 I/M/A/C/F/D/P ISA supported
RISC-V standard interrupts supported, including software,
timer and external interrupts
CPU Core
6-Stage Pipeline
Configurable Dynamic Branch Prediction unit
Configurable Prefetch Unit
Configurable interrupt numbers, levels and priorities
Vectored fast interrupts supported
Privileged
Modes
Machine-Mode supported
User-Mode supported
Nested interrupts supported
Interrupt tail-chaining supported
Supervisor-Mode supported
NMI
FPU
DSP
NMI (Non-Maskable Interrupt) supported
Caches
I-Cache, configurable Cache size, N-way, Cache Line Size 32Bytes
D-Cache, configurable Cache size, 2-way, Cache Line Size 32Bytes
Single/double-precision supported (F, D extensions)
SIMDPartial-SIMD64-bit and Non-SIMD DSP instructions
(P extension)
Bus Interfaces
64-Bit AXI System Bus Interface
32-Bit AHB-lite (Private Peripheral Interface)
64-Bit ILM Bus Interface
MMU
Configurabel MMU (memory management unit)
Supported 2-level TLBs, configurable TLB entries
64-Bit AXI Slave Port
Low Power
WFIWait For Interruptand WFEWait For Event
Supported
2 32-Bit DLM Bus Interface
Debug
Standard IEEE 4-wire JTAG supported
Configurable Hardware Breakpoints
Sleep and Deep Sleep Mode Supported
NICE
Extension
Allowing customers to add user-defined instructions
Implementing application specific hardware co-unit based
on NICE interface
Security
Configurable PMP (Physical Memory Protection) feature
Configurable TEE (Trusted Execution Environment) feature
Timer
Tool Kit
Configurable 64-bit private timer
Standard RISC-V Toolchain supported
Linux/Windows IDE (Integrated Development Environment)
supported
UX600 Series Diagram
JTAG
UX600 Core Wrapper
DEBUG
TIMER
UX600
Extend
Instructions
ECLIC
IRQ
MMU
uCore
Misc Ctrl
NICE IF
NMI
DSP/
FPU
ICache DCache
I-IF
D-IF
BIU
LM Ctrl
Private Peripheral IF
(AHB-Lite)
System Bus IF
(AXI)
ILM IF
DLM IF
(SRAM)
Slave Port
(AXI)
(
SRAM)
Peripheral Bus
System Bus
ILM
DLM
Ext
MEM
Per
1
Per
2
Per
3
SRAM