RISC-V CPU IP Solution

600
Series 32-Bit & 64-Bit High Performance Processor
600 Series processors include four different classes: N600 (32 bit), U600 (32 bit + MMU), NX600 (64 bit) and UX600 (64 bit + MMU). With MMU, UX600 supports heavyload operating systems such as Linux. 600 Series can be applied to edge computing, data center, networking, etc.
600 Core Complex
Debug
600 Core
Crypto
VPU
MMU
NMI
ECLIC
Timer
WFI/WFE
NICE
FPU
DSP
MUL/DIV
600 uCore
ICache
DCache
TEE
PMP
ILM
DLM
AHB-Lite
AXI
  • Real-time Feature
  • RV32 IMACFDBPKVZfh/Zcxlcz
    RV64 IMACFDPBKVZfh/Zc
  • 6 Stage Pipeline
    Dual-issue
  • I/D Cache
  • Security(PMP, TEE)
  • SP/DP FPU
  • NICE Extension
  • AXI system bus
  • RISC-V Standard
    Debug
  • JTAG & 2-wire JTAG
  • Low Latency Interrupt
  • Full Dev Kit & SDK
Cluster Interrupt Module PLIC
Cluster Debug Module JTAG/ cJTAG
core 0
DSP/FPU/VPU
ICache w/ECC
DCache w/ECC
Core
Machine/Supervisor/User Mode
MMU
PMP
ECLIC
NICE IF
ILM w/ECC
DLM w/ECC
core 1
DSP/FPU/VPU
ICache w/ECC
DCache w/ECC
Core
Machine/Supervisor/User Mode
MMU
PMP
ECLIC
NICE IF
ILM w/ECC
DLM w/ECC
core 2
DSP/FPU/VPU
ICache w/ECC
DCache w/ECC
Core
Machine/Supervisor/User Mode
MMU
PMP
ECLIC
NICE IF
ILM w/ECC
DLM w/ECC
core n
DSP/FPU/VPU
ICache w/ECC
DCache w/ECC
Core
Machine/Supervisor/User Mode
MMU
PMP
ECLIC
NICE IF
ILM w/ECC
DLM w/ECC
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Slave Port
Snoop Filte
Snoop Control Unit
IOCP
...
IOCP
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Cluster Cache
128KB-4MB
|
Configurable CLM
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Cluster Memory Ports
Cluster Peripheral Ports
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600 Series Single Core Features
  • RISC-V RV32 IMACFDBPKVZfh/Zcxlcz and RV64 IMACFDPBKVZfh/Zc ISA supported
  • Dual Issue, in-order 6 stage Harvard Pipeline
  • 64-bit AXI system bus, configurable 32-bit AHB-Lite slave port
  • Double, Single and Half-Precision floating point
  • Configurable SIMD DSP Extension
  • Full Vector Extension with 128-b VLEN
  • Configurable ILM/DLM (Instruction Local Memory) with ECC
  • Configurable ICachewith ECC
  • Configurable DCache with ECC
  • Configurable MMU supported (SV32/SV39/SV48)
  • PMP and TEE supported to meet the system security requirement
  • Full standard debug function with JTAG and cJTAG
  • Full standard RISC-V toolchain with Linux\Windows IDE supported
600 series SMP Multi Core Features
  • Dual-mode feature supported (Application Processor mode and Real-time Processor mode)
  • Up to 16 SMP cores in one Cluster
  • SoC Connectivity
    • Configurable Cluster Memory Port(64/128/256/512-bit)
    • Cluster Peripheral Ports support 32-bit AHB-Lite protocol
  • Up to 16 IOCP (I/O Coherent Port) Ports supported
  • Support Hardware Data Prefetching mechanism
  • Cluster Cache
    • Configurable Cluster Cache size
    • Configurable Cacheline size（64Bytes）
    • Configurable multi-cycle Tag RAM and Data RAM
    • Support cacheline LOCK, FLUSH and INVAL operations
    • 16-way associative
    • Can be configured to Cluster Local Memory
600 Series Performance and Configuration Options
Nuclei CPU IP N600 U600 NX600 UX600 600-SMP
Pipeline Stages 6
Issue-Width Single-Issue Single-Issue Single-Issue Single-Issue Single-Issue
User Mode & PMP(MPU) Configurable Configurable Configurable Configurable Configurable
Hardware Multiplier and Divider Configurable Configurable Configurable Configurable Configurable
Half-Precision/Single-Precision/Double-Precision FPU Configurable Configurable Configurable Configurable Configurable
Instruction Cache Configurable Configurable Configurable Configurable Configurable
Data Cache Configurable Configurable Configurable Configurable Configurable
Digital Signal Processing (DSP) Configurable Configurable Configurable Configurable Configurable
NICE Configurable Configurable Configurable Configurable Configurable
ILM Configurable Configurable Configurable Configurable Configurable
DLM Configurable Configurable Configurable Configurable Configurable
TEE Configurable Configurable Configurable Configurable Configurable
Vector Extension Configurable Configurable Configurable Configurable Configurable
Cluster Cache No No No No Configurable
MMU No Configurable No Configurable Configurable
SMP Configurable Configurable Configurable Configurable Configurable
Crypto Configurable Configurable Configurable Configurable Configurable
Customer Cases
ECU master control (ASIL-D level)
  • 400+MHz, 900 automotive-grade Dual-core Lockstep CPU
  • HSM (encryption hardware acceleration engine + N205 CPU, etc.)
  • Both the storage unit and the bus have ECC (32+6) error correction function
Xuanyuan 1030 series

30G Layer 2 Ethernet Switch Chip

  • 500MHz, UX608 with TEE supports Linux or UCOS dual mode
  • Integrated 8-way Gigabit electrical port PHY, 2-way 10G Serdes+4-way 1G Serdes and other interfaces
  • Support flexible service port selection to meet various application scenarios
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RISC-V Foundation

SICA

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