RISC-V CPU IP Solution

600
Series 32-Bit & 64-Bit High Performance Processor
600 series processors include three products: N600 (32-bit), nx600 (64 bit) and ux600 (64 bit + MMU).Aim at AIoT edge computing, real-time control and high-performance embedded applications.It is suitable to AI, storage, smart TV, broadband gateway and other application scenarios.
N600 Core Complex
Debug
N600 Core
MMU
NMI
ECLIC
Timer
WFI/WFE
NICE
FPU
DSP
MUL/DIV
600 uCore
Cluster Cache
I/DCache
TEE
PMP
ILM
DLM0/DML1
AHB-Lite
AXI
  • High Real-TimePerformance
  • RV32/64 IMACFDPB
  • 6 Stage Pipeline Dual-issue
  • I/D Cache
  • Security(PMP,TEE)
  • NICE Extension
  • SP/DP FPU & DSP
  • AXI system bus
  • RISC-V Standard Debug
  • JTAG & 2-wire JTAG
  • Low Latency Interrupt
  • Full Development Toolkit
  • RV32/64 IMACFDPB supported
  • 6 Stage Pipeline
  • Configurable dual-mode feature (real-time processor and application processor)
  • 64/128-bit AXI system bus, AHB-Lite peripheral port, ILD/DLM interface and slave interface
  • Configurable data and instruction SRAM
  • Configurable Instruction-Cache with ECC
  • Configurable Data-Cache with ECC
  • Configurable Cluster Cache
  • Cache Line Size is 32Bytes or 64Bytes
  • MMU supported
  • NICE supported
  • Double, Single and Half-Precision floating point and DSP SIMD Extension
  • TEE supported to meet the system security needs
  • Full Standard Debug Function with JTAG/cJTAG Port
  • Full Standard RISC-V Toolchain, and Linux\Windows IDE supported
Comparisons to Cortex-R4、R5 Comparisons to Cortex-R4、R5 Comparisons to Cortex-R4、A7
Nuclei CPU IP N600 NX600 UX600
Dhrystone(DMIPS/MHz) 1.64/4.09(Legal/Best Effort) 1.75/4.91(Legal/Best Effort)
CoreMark(CoreMarks/MHz) 3.51 3.20
流水线级数 6
Pipeline Stages Configurable Configurable Configurable
User Mode & PMP(MPU) Configurable Configurable Configurable
Hardware multiplier and divider Configurable Configurable Configurable
Single-Precision/Double-Precision FPU Configurable Configurable Configurable
Instruction-Cache Configurable Configurable Configurable
Data-Cache Configurable Configurable Configurable
Digital Signal Processing (DSP) Configurable Configurable Configurable
NICE Configurable Configurable Configurable
TEE No No No
Vector Extension Configurable Configurable Configurable
Cluster Cache No No Configurable
MMU No No No
Customer Case

Highly secure and reliable embedded network processor


  • 800MHz, AMP dual-core UX608 running Linux operating system
  • HSM (Cryptographic hardware acceleration engine + N205 Lockstep RISC-V CPU, etc.)
  • Rich storage architecture + network interface
  • Support secure boot and provide Linux/RTOS/Bare-Metal 3-level SDK

30G Layer 2 Ethernet Switch Chip


  • 500MHz, UX608 with TEE supports Linux or UCOS dual mode
  • Integrated 8-way Gigabit electrical port PHY, 2-way 10G Serdes+4-way 1G Serdes and other interfaces
  • Support flexible service port selection to meet various application scenarios
Partners(排名不分先后)

RISC-V Foundation

SICA

China RISC-V Industry Alliance

China RISC-V Alliance

武汉光电工业技术研究院

HBSIA

CBSIA

Amlogic

VeriSilicon

LAUTERBACH

TencentOS Tiny

OpenHarmony

PlatformIO

SEGGER

TrustKernel

XIAOMI

RT-Thread

OPEN AI LAB

AnLogic

ASR

GigaDevice

XinSheng Tech

TIH Microelectronics

FisiLink

Witeme

ChipIntelli

Geoforce Chip

TAOLINK TECHNOLOGIES

Huazhong University of Science and Technology

Shanghai Jiao Tong University

Wuhan University

Hubei University of Technology

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