RISC-V CPU IP Solution

600
Series 32-Bit & 64-Bit High Performance
600 series processors include four products: N600 (32 bit), U600 (32 bit + MMU), NX600 (64 bit) and UX600 (64 bit + MMU). Aim at AIoT edge computing, real-time control and high-performance embedded applications. It is suitable to AI, storage, smart TV, broadband gateway and other application scenarios.
600 Core Complex
Debug
600 Core
MMU
NMI
ECLIC
Timer
WFI/WFE
NICE
FPU
DSP
MUL
DIV
600 uCore
ICache
DCache
TEE
PMP
ILM
DLM
AHB-Lite
AXI
  • Real-time Feature
  • RV32
    IMACFDPBKZfh/Zcxlcz
    RV64
    IMACFDPBKZfh/Zc
  • 6 Stage Pipeline
    Dual-issue
  • I/D Cache
  • Security(PMP, TEE)
  • AXI system bus
  • RISC-V Standard Debug
  • JTAG & 2-wire JTAG
  • Low Latency Interrupt
  • Full Dev Kit & SDK
  • RISC-V RV32 IMACFDPBKZfh/ZcxlczRV64 IMACFDPBKZfh/Zc ISA supported
  • Single Issue, in-order 6 stage Harvard Pipeline
  • 64-bit AXI system bus, configurable 32-bit AHB-Lite slave port
  • Double, Single and Half-Precision floating point
  • ConfigurableSIMD DSP Extension
  • Configurable Instruction and Data Memory
  • Configurable ILM (Instruction Local Memory) with ECC
  • Configurable DLM (Data Local Memory) with ECC
  • ConfigurableMMU supported(SV32/SV39)
  • PMP supported and TEE supported to meet the system security needs
  • Full Standard Debug Function with JTAG and cJTAG Port
  • Full Standard RISC-V Toolchain, and Linux\Windows IDE supported
600 Series Performance and Configurability
Nuclei CPU IP N600 U600 NX600 UX600
Dhrystone(DMIPS/MHz) 1.789/4.344(Legal/Best Effort) 2.047/5.579(Legal/Best Effort)
CoreMark(CoreMarks/MHz) 3.665 3.79
Pipeline Stages 6
Issue Single-Issue Single-Issue Single-Issue Single-Issue
User Mode & PMP(MPU) Configurable Configurable Configurable Configurable
Hardware multiplier and divider Configurable Configurable Configurable Configurable
Single-Precision/Double-Precision FPU Configurable Configurable Configurable Configurable
Instruction-Cache Configurable Configurable Configurable Configurable
Data-Cache Configurable Configurable Configurable Configurable
Digital Signal Processing (DSP) Configurable Configurable Configurable Configurable
NICE Configurable Configurable Configurable Configurable
ILM Configurable Configurable Configurable Configurable
DLM Configurable Configurable Configurable Configurable
PMP No No No No
MMU No Configurable No Configurable
Customer Case

Highly secure and reliable embedded network processor


  • 800MHz, AMP dual-core UX608 running Linux operating system
  • HSM (Cryptographic hardware acceleration engine + N205 Lockstep RISC-V CPU, etc.)
  • Rich storage architecture + network interface
  • Support secure boot and provide Linux/RTOS/Bare-Metal 3-level SDK

30G Layer 2 Ethernet Switch Chip


  • 500MHz, UX608 with TEE supports Linux or UCOS dual mode
  • Integrated 8-way Gigabit electrical port PHY, 2-way 10G Serdes+4-way 1G Serdes and other interfaces
  • Support flexible service port selection to meet various application scenarios
Partners(排名不分先后)

RISC-V Foundation

SICA

China RISC-V Industry Alliance

China RISC-V Alliance

武汉光电工业技术研究院

HBSIA

CBSIA

SZICC

Amlogic

VeriSilicon

LAUTERBACH

TencentOS Tiny

OpenHarmony

PlatformIO

SEGGER

TrustKernel

XIAOMI

taolink-tech

GeoforceChip

ChipIntelli

Witmem

Fisilink

TIH Microelectronics

XinSheng Tech

GigaDevice

ASR

AnLogic

TusStar

Mocro & Nano Institute

RT-Thread

OPEN AI LAB

IAR

HUST

SJTU

WHU

HBUT

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