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中文
Home
Products
RISC-V CPU IP
Nuclei SoC IP
Subsystem Solution
HSM Subsystem
Automotive Subsystem
AI Subsystem
WiFi Subsystem
News
Company News
Product News
Resources
Development Boards
Chip Development Board
FPGA Development Board
Debugger
Docs & Tools
Tools Download
Docs Center
About
Company
Join US
Contact
RISC-V MCU
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RISC-V CPU IP Solution
Nuclei Core Gen
FREQ(MHZ)
TECH
GEN_METHOD
Default
Area Optimized
Performance Optimized
Core Type
900
900-SMP
SMP
Core Number :
L2 Size :
64K
128K
256K
512K
1MB
2MB
4MB
Tag Ram cycle :
Data Ram cycle :
Bus Width :
64
128
IOCP Number :
IOCP SALVE IDW :
8
16
CLM Slave :
CLM Slave IDW :
8
16
ISA
RV32
RV64
PA Size
PMP
PMP
PMP Entry Number :
8
16
TEE
TEE
Multiply
2-cyc Myltiply
3-cyc Myltiply
4-cyc Myltiply
Divider
17-cyc Divider
9-cyc Divider
18-cyc Divider
34-cyc Divider
B-Extension
B-Extension
K-Extension
K-Extension
F/D-Extension
Not Supported
Single FPU
Double FPU
Half FPU
DSP
DSP
VPU
VPU
VLEN :
128
256
512
Fully Parallel
VPU Port
Addr Width
ILM
ILM
ILM Addr Width :
DLM
DLM
DLM Addr Width :
External Access ILM/DLM
External Access ILM/DLM
SLV IDW :
CLIC
CLIC
MMU
MMU
TLB Entry Number :
128
256
512
1024
ICache
ICache
8K
16K
32K
64K
DCache
DCache
8K
16K
32K
64K
Device Region
Device Region
Non-Cacheable Region
Non-Cacheable Region
ECC
ECC
Private Peripheral Bus
Private Peripheral Bus
Interrupt Number
Nice (Nuclei Instruction Custom Extension)
Nice (Nuclei Instruction Custom Extension)
Etrace
Etrace
查看大图