RISC-V CPU IP Solution

NA300
32-Bit Automotive Processor
NA300 series processor is a ISO26262 ASIL-B/D Certified RISC-V CPU IP,Nuclei self-developed STL supports multiple ASIL-B automotive use cases.
N300 Core
WFI/WFE
Debug
4-Wire JTAG/2-Wire cJTAG
ZC
ECLIC
Timer
MUL/DIV
FPU
DSP
N300 uCore
PMP
TEE
ILM
DLM
ICache
DCache
AHB-Lite
APB
Fast-IO
  • Great Power Efficiency
  • RV32IMACFD
    BPC/Zcxlcz
  • 3-stage Pipeline
    Dual-issue
  • Machine, User, Supervisor-Mode
  • Security (PMP)
  • AHB-Lite System Bus
  • RISC-V Standard Debug
  • JTAG & cJTAG
  • Low Latency Interrupt
  • Full Dev Kit & SDK
  • RV32IMACFDBPC/Zcxlcz ISA supported
  • Dual-issue, in-order 3 stage Harvard Pipeline
  • Support fast interrupts tail-chaining mechanism , vectored interrupt processing mode for extremely fast interrupt response, and interrupt preemptions based on interrupt levels.
  • Configurable ILM/DLM
  • Configurable Instruction-Cache
  • Configurable Data-Cache
  • Support single/double float and SIMD DSP.
  • Support TEE
  • Configurable Issue
  • Full Standard Debug Function with JTAG port.
  • Full Standard RISC-V Toolchain, and Linux/Windows IDE supported
Download NA300 Product Brief
NA300 is a ISO26262 ASIL-B/D Certified RISC-V CPU IP
NA300D Serires
  • Systematic Capability:ASIL D
  • Hardware Safe ty Integrity: ASIL D in DCLS mode
NA300B Serires
  • Systematic Capability:ASIL D
  • Hardware Safe ty Integrity: ASIL B
  • Nuclei self developed Softwate Test Library for ASIL B application
  • Fault Injection simulation FMEDA report for configurable design
  • ASIL B support fot both split mode and singlecore mode
  • Safety enhanced hardware for trade-off between diagnostic coverage and hardware cost
Download NA300 Certificate
Summary for Nuclei Automotive FuSa Solutions
  • ASIL-B & ASIL-D solutions are both available for NA300 & NA900 series
  • Rich configurations to fit variable automotive SoC requirements
  • Comprehensive safety package
    • Adaptable Safety Manual
    • Adaptable Safety Analysis Report
    • Supporting Evidence
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