RISC-V CPU IP Solution

NS
32-Bit Nuclei Security processor
NS100 Single Core Configuration Features
  • RISC-V RV32I(E)MC/Zc ISA supported
  • Single Issue, in-order 2 stage Harvard Pipeline
  • Configurable single cycle and multiple cycle Multiplier
  • 32 AHB-Lite/ICB system bus
  • Machine mode
  • Configurable interrupt controller
  • Full Standard Debug Function with JTAG/cJTAG Port
NS300 Single Core Configuration Features
  • RISC-V RV32IMACFDB ISA supported
  • In-order 6 stage Harvard Pipeline
  • Single/Dual Issue
  • Double and Single Precision floating point
  • Configurable ILM (Instruction Local Memory)
  • Configurable DLM(Data Local Memory) with ECC
  • Configurable I-Cache & D-Cache with ECC, 512B-64KB
  • Configurable 32b AHB-Lite system bus
  • Configurable 32-bit AHB slave port
  • Besides Machine mode & User mode, Supervisor mode is suppored for TEE (Trust Execution Environment)
  • Configurable NICE Interface for User-Defined Extensions
  • Configurable ECLIC
  • Full Standard Debug Function with JTAG/cJTAG Port
NS600 Single Core Configuration Features
  • RISC-V RV32IMACF ISA supported
  • Single-Precision floating point
  • Configurable ILM (Instruction Local Memory)
  • Configurable DLM0/DLM1 (Data Local Memory) with ECC
  • Configurable I-Cache with ECC, 16-64KB
  • Configurable D-Cache with ECC, 16-64KB
  • Configurable 64b AXI system bus
  • Configurable 64-bit AXI slave port
  • Besides Machine mode & User mode, Supervisor mode is suppored for TEE (Trust Execution Environment)
  • Configurable ECLIC
  • TEE supported
  • Full Standard Debug Function with JTAG/cJTAG Port
NS100 vs NS300 vs NS600
Security Features NS100 NS300 NS600
Data Parity Protection Yes Yes Yes
Datapath Polarity Yes Yes Yes
Core Key Status Lock Yes Yes Yes
Core Key Status Clear Yes Yes Yes
Secure Status Monitor Yes Yes Yes
Consistent Instruction Execution Latency Yes Yes Yes
Vectored Interrupt Remapping Yes Yes Yes
Secure Debug Yes Yes Yes
Instruction Execution Monitor Interface Yes Yes Yes
Value Write-back to Junk Register Yes Yes
Random Instruction Injection Yes Yes
Architectural Clock Gate Override Yes Yes
Power Scrambling on Idle Function Unit Yes Yes
MPU Yes Yes
Stack Check Yes Yes
Partners(排名不分先后)

RISC-V Foundation

SICA

China RISC-V Industry Alliance

China RISC-V Alliance

武汉光电工业技术研究院

HBSIA

CBSIA

SZICC

Amlogic

VeriSilicon

LAUTERBACH

TencentOS Tiny

OpenHarmony

PlatformIO

SEGGER

TrustKernel

XIAOMI

taolink-tech

GeoforceChip

ChipIntelli

Witmem

Fisilink

TIH Microelectronics

XinSheng Tech

GigaDevice

ASR

AnLogic

TusStar

Mocro & Nano Institute

RT-Thread

OPEN AI LAB

IAR

HUST

SJTU

WHU

HBUT

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