PCIe
Core Features
This document is the PCIE Controller IP (PCIe Controller)’s user manual. PCIe Controller is a high performance PCIE controller, it can support PCIE 1.0/2.0/3.0/4.0 protocol, and the support speed is 2.5G/5G/8G/16G. PCIe Controller support dual mode (ROOT mode or Endpoint mode).PCIe Controller’s interface with PHY is PIPE 4.0 interface and the PCIe Controller’s interface with application layer is the AXI4.0 interface, and it also has a APB bus for register access.The Lane number is configable, it can support X1, X2, X4 lanes.
  • Support AXI master and AXI slave interface for data transfer
  • Support up to 4 lanes
  • Support Gen1 2.5G, Gen2 5G, Gen3 8G speed, Gen4 16G speed
  • Designed for Rootport and Endpoint. Can be configured to acted as RC or EP
  • 32, 64, 128 bit data support for AXI master and AXI slave interface. axsize can be 0,1,2,3,4
  • Support Equalization negotiation for Gen3 and Gen4
  • Internal address translation units
  • Advanced Error reporting (AER) capability support
  • Resize Bar capability supprt
  • LTR function support
  • Lane reversal and Lane borken replace support
  • Support Async between AXI and PCIE core clock domain
  • MSI and INT interrupt message support
  • support PIPE 4.0
  • support power management L0s, L1, L1 substates, L2
  • support CLKREQ# function to turn off pll reference clock for power management
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