900 Series 32-Bit/64-bit processor_Nuclei-Best RISC-V Processor IP

RISC-V CPU IP Solution

900

Series 32-Bit & 64-Bit High Performance Processor

900 Series processors include four different classes: N900 (32 bit), U900 (32 bit + MMU), NX900 (64 bit) and UX900 (64 bit + MMU). With MMU, UX900 supports heavyload operating systems such as Linux. 900 Series can be applied to edge computing, data center, networking, etc.

900 Core Complex

Debug

900 Core

VPU

MMU

NMI

ECLIC

Timer

WFI/WFE

NICE

FPU

DSP

MUL/DIV

900 uCore

ICache

DCache

TEE

PMP

ILM

DLM

AHB-Lite

AXI

Real-time Feature
RV32
IMACFDPBVK/Zcxlcz
RV64
IMACFDPBVK/Zc
9 Stage Pipeline
Dual-issue
I/D Cache
Machine, User,
Supervisor-Mode
Security(PMP, TEE)
NICE Extension
AXI system bus
RISC-V Standard
Debug
JTAG & 2-wire JTAG
Low Latency Interrupt
Full Dev Kit & SDK

900-SMP(multi-core) is the configurable version of 900 Series support symmetric multi-processor (SMP) configuration.

Cluster Interrupt Module ECLIC/ PLIC

Cluster Debug Module JTAG/ cJTAG

core 0

DSP/FPU/VPU

ICache w/ECC

DCache w/ECC

Core

Machine/Supervisor/User Mode

MMU

PMP

NICE IF

ILM w/ECC

DLM w/ECC

core 1

DSP/FPU/VPU

ICache w/ECC

DCache w/ECC

Core

Machine/Supervisor/User Mode

MMU

PMP

NICE IF

ILM w/ECC

DLM w/ECC

core 2

DSP/FPU/VPU

ICache w/ECC

DCache w/ECC

Core

Machine/Supervisor/User Mode

MMU

PMP

NICE IF

ILM w/ECC

DLM w/ECC

core n

DSP/FPU/VPU

ICache w/ECC

DCache w/ECC

Core

Machine/Supervisor/User Mode

MMU

PMP

NICE IF

ILM w/ECC

DLM w/ECC

Slave Port

Snoop Filte

Snoop Control Unit

IOCP

...

IOCP

AXI4

Cluster Cache
128KB-4MB

Configurable CLM

AXI4

Cluster Memory Ports

Cluster Peripheral Ports

AHB-Lite

AXI4

900 Series Single Core Features

RISC-V RV32 IMACFDPBVK/Zcxlcz and RV64 IMACFDPBVK/Zc ISA supported
Dual Issue, in-order 9 stage Harvard Pipeline
64-bit AXI system bus, configurable 32-bit AHB-Lite slave port
Double, Single and Half-Precision floating point
Configurable SIMD DSP Extension
Full Vector Extension with configurable VLEN & DLEN
Configurable ILM (Instruction Local Memory) with ECC
Configurable ILM (Instruction Local Memory) with ECC
Configurable DLM (Data Local Memory) with ECC
Configurable MMU supported (SV32/SV39/SV48)
PMP and TEE supported to meet the system security requirement
Full standard debug function with JTAG and cJTAG
Full standard RISC-V toolchain with Linux\Windows IDE supported

900 series SMP Multi Core Features

Dual-mode feature supported (Application Processor mode and Real-time Processor mode)
Up to 16 SMP cores in one Cluster
SoC Connectivity
- Configurable Cluster Memory Port(64/128/256/512-bit)
- Cluster Peripheral Ports support 32-bit AHB-Lite protocol
Up to 16 IOCP (I/O Coherent Port) Ports supported
Support Hardware Data Prefetching mechanism
Cluster Cache
- Configurable Cluster Cache size
- Configurable Cacheline size（64Bytes）
- Configurable multi-cycle Tag RAM and Data RAM
- Support cacheline LOCK, FLUSH and INVAL operations
- 16-way associative
- Can be configured to Cluster Local Memory

Common Configurations and Applications of 900 Series

N900 Core Machine/Supervisor/
User Mode

ILM

DLM

DSP/FPU

32b architecture, 9-stage pipeline
Dual-issue configurable
RV32 IMACFDPBVK/Zcxlcz
On chip instruction and data local memory
SMP up to 16 cores

MCU

AIoT

Automotive Electronics

U900 Core Machine/Supervisor/
User Mode

ICache w/ECC

DCache w/ECC

FPU/VPU

MMU

32b architecture, 9-stage pipeline
Dual-issue configurable
RV32 IMACFDPBVK/Zcxlcz
16-64KB instruction and data cache
Support MMU, able to run Linux
SMP up to 16 cores

32b Linux

Security

NX900 Core Machine/Supervisor/
User Mode

ILM

DLM

ICache w/ECC

DCache w/ECC

DSP/FPU/VPU

64b architecture, 9-stage pipeline
Dual-issue configurable
RV64 IMACFDPBVK/Zc
On chip instruction and data local memory
16-64KB instruction and data cache
SMP up to 16 cores

AR/VR

Storage

UX900 Core Machine/Supervisor/
User Mode

ILM

DLM

ICache w/ECC

DCache w/ECC

DSP/FPU/VPU

Cluster Cache

MMU

64b architecture, dual-issue 9-stage pipeline
RV64 IMACFDPBVK/Zc
On chip instruction and data local memory
16-64KB instruction and data cache
Support MMU, able to run Linux
SMP up to 16 cores
Cluster Cache configurable, support cache coherence

64b Linux

Application Processor

ADAS+robotics

Download 900 Product Brief

900 Series Performance and Configuration Options

Nuclei CPU IP	N900	U900	NX900	UX900
Dhrystone (DMIPS/MHz)	2.84/6.05(Legal/Best Effort)		3.09/7.7(Legal/Best Effort)
CoreMark (CoreMarks/MHz)	5.5
Pipeline Stages	9
Issue-Width	Dual-Issue	Dual-Issue	Dual-Issue	Dual-Issue
User Mode & PMP(MPU)	Configurable	Configurable	Configurable	Configurable
Hardware Multiplier and Divider	Configurable	Configurable	Configurable	Configurable
Half-Precision/Single-Precision/Double-Precision FPU	Configurable	Configurable	Configurable	Configurable
Instruction Cache	Configurable	Configurable	Configurable	Configurable
Data Cache	Configurable	Configurable	Configurable	Configurable
Digital Signal Processing (DSP)	Configurable	Configurable	Configurable	Configurable
NICE	Configurable	Configurable	Configurable	Configurable
ILM	Configurable	Configurable	Configurable	Configurable
DLM	Configurable	Configurable	Configurable	Configurable
TEE	Configurable	Configurable	Configurable	Configurable
Vector Extension	Configurable	Configurable	Configurable	Configurable
Cluster Cache	Configurable	Configurable	Configurable	Configurable
MMU	No	Configurable	No	Configurable
Multi-Processors	Configurable	Configurable	Configurable	Configurable