RISC-V CPU IP Solution

900
Series 32-Bit & 64-Bit High Performance Processor
900 series processors include three products: N900 (32-bit), nx900 (64 bit) and ux900 (64 bit + MMU). With MMU, ux900 can run heavy operating systems, such as Linux. It is very suitable for replacing ARM cortex-m7, R7, R8, A35, A53, A55, which can be applied to AIoT edge computing, data center, network equipment, and other fields.
900 Core Complex
Debug
900 Core
Cluster Cache
VPU
MMU
NMI
ECLIC
Timer
WFI/WFE
NICE
FPU
DSP
MUL/DIV
900 uCore
ICache
DCache
TEE
PMP
ILM
DLM0/DML1
AHB-Lite
AXI
  • High Real-TimePerformance
  • RV32 IMACFDPB RV64 IMACFDPB
  • 9 Stage Pipeline Dual-issue
  • I/D Cache
  • Machine, User,Supervisor-Mode
  • Security(PMP,TEE)
  • NICE Extension
  • AXI system bus
  • RISC-V Standard Debug
  • JTAG & 2-wire JTAG
  • Low Latency Interrupt
  • Full Development Toolkit
  • RISC-V RV32/64 IMACFDPVBZfh ISA supported
  • Dual Issue, in-order 9 stage Harvard Pipeline
  • Single core, AMP or SMP supported
  • SMP support
  • 64/128-bit AXI system bus, configurable 64-bit AXI slave port
  • Double, Single and Half-Precision floating point and DSP Extension
  • Full Vector Extension with configurable VLEN & DLEN
  • Configurable Instruction and Data Memory
  • Configurable ILM (Instruction Local Memory) & DLM (Data Local Memory) with ECC
  • Configurable Cluster Cache with ECC
  • Configurable Vector Extension（128/256/512bit）
  • MMU supported
  • TEE supported to meet the system security needs
  • Full Standard Debug Function with JTAG Port
  • Full Standard RISC-V Toolchain, and Linux\Windows IDE supported
Comparisons to Cortex-M7、R7、R8 Comparisons to Cortex-M7、R7、R8 Comparisons to Cortex-A35、A53、A9 Comparisons to Cortex-R8、A35、A53、A55
Nuclei CPU IP N900 NX900 UX900 900-MC
Dhrystone(DMIPS/MHz) 2.67/5.64(Legal/Best Effort) 3.06/7.49(Legal/Best Effort)
CoreMark(CoreMarks/MHz) 6.04 5.97
Pipeline Stages 9
User Mode & PMP(MPU) Configurable Configurable Configurable Configurable
Hardware multiplier and divider Configurable Configurable Configurable Configurable
Single-Precision/Double-Precision FPU Configurable Configurable Configurable Configurable
Instruction-Cache Configurable Configurable Configurable Configurable
Data-Cache Configurable Configurable Configurable Configurable
Digital Signal Processing (DSP) Configurable Configurable Configurable Configurable
NICE Configurable Configurable Configurable Configurable
TEE Configurable Configurable Configurable Configurable
Vector Extension Configurable Configurable Configurable Configurable
Cluster Cache Configurable Configurable Configurable Configurable
MMU No No Configurable Configurable
Multi-Processors No No No Configurable
Customer Case
ECU master control (ASIL-D level)
  • 400+MHz, 900 automotive-grade Dual-core Lockstep CPU
  • HSM (encryption hardware acceleration engine + N205 CPU, etc.)
  • Both the storage unit and the bus have ECC (32+6) error correction function
Partners（排名不分先后）

RISC-V Foundation

SICA

China RISC-V Industry Alliance

China RISC-V Alliance

武汉光电工业技术研究院

HBSIA

CBSIA

Amlogic

VeriSilicon

LAUTERBACH

TencentOS Tiny

OpenHarmony

PlatformIO

SEGGER

TrustKernel

XIAOMI

taolink-tech

GeoforceChip

ChipIntelli

Witmem

Fisilink

TIH Microelectronics

XinSheng Tech

GigaDevice

ASR

AnLogic

TusStar

Mocro & Nano Institute

BEIJING ACADEMY OF EDGE COMPUTING

RT-Thread

OPEN AI LAB

IAR

HUST

SJTU

WHU

HBUT

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